Customizing Floating-Point Operators for Linear Algebra Acceleration on FPGAs

Accelerating the execution of algorithms involving floating-point computations is currently a necessity in the scientific community. A solution – FPGAs – are believed to provide the best balance between costs, performance and flexibility. The FPGA’s flexibility can be best exploited when used to accelerate ”exotic operators”(log, exp, dot product) and operators tailored for the numerics of each application. These requirements gave birth to FloPoCo, a floating-point core generator written in C++ available under GPL at 1. The purpose of this work was to bring FloPoCo to maturity, by framework stabilization and operator implementation. In term of framework stabilization we have implemented a novel automatic pipeline generation feature. In term of implemented operators, our work includes the basic blocks of FloPoCo: IntAdder, IntMultiplier, FPMultiplier, DotProduct, Karatsuba multiplication, FPAdder, LongAccumulator. The obtained results are promising, ranking higher than the results obtained by FPLibrary 2 and not far from the operators generated with Xilinx CoreGen 3. However, we generate portable VHDL code which is target independent, while CoreGen work only with Xilinx FPGAs. Nevertheless, work is still needed to bring some operators to CoreGen level. We also studied the possibilities to implement interval arithmetic operators on FPGAs. We have proposed and discussed architectures for the four basic operations, for both infimum-supremum and midpoint-radius representations. We have also proposed an application for testing different trade-offs in terms of precision and size of these operators. 1http://www.ens-lyon.fr/LIP/Arenaire/Ware/FloPoCo 2http://www.ens-lyon.fr/LIP/Arenaire/Ware/FPLibrary/ 3http://www.xilinx.com/ipcenter/coregen